regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr, IA64_PSR_CPL0_BIT);
if (PSCB(v, dcr) & IA64_DCR_BE)
regs->cr_ipsr |= IA64_PSR_BE;
-
+ else
+ regs->cr_ipsr &= ~IA64_PSR_BE;
+
if (PSCB(v, hpsr_dfh))
regs->cr_ipsr |= IA64_PSR_DFH;
PSCB(v, vpsr_dfh) = 0;
regs->cr_ipsr = vcpu_pl_adjust(regs->cr_ipsr, IA64_PSR_CPL0_BIT);
if (PSCB(v, dcr) & IA64_DCR_BE)
regs->cr_ipsr |= IA64_PSR_BE;
+ else
+ regs->cr_ipsr &= ~IA64_PSR_BE;
+
if (PSCB(v, hpsr_dfh))
regs->cr_ipsr |= IA64_PSR_DFH;
IA64_PSR_CPL0_BIT);
if (PSCB(current, dcr) & IA64_DCR_BE)
regs->cr_ipsr |= IA64_PSR_BE;
+ else
+ regs->cr_ipsr &= ~IA64_PSR_BE;
+
if (PSCB(current, hpsr_dfh))
regs->cr_ipsr |= IA64_PSR_DFH;